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19-3223; Rev 0; 2/04
KIT ATION EVALU ABLE AVAIL
Ultra-Low-Power, High-DynamicPerformance, 60Msps Analog Front End
General Description Features
Integrated Dual, 8-Bit ADCs and Dual, 10-Bit DACs Ultra-Low Power 80mW at fCLK = 60MHz (Rx Mode) 52.5mW at fCLK = 60MHz (Tx Mode) Low-Current Idle and Shutdown Modes Excellent Dynamic Performance 48dB SINAD at fIN = 25MHz (ADC) 64.2dBc SFDR at fOUT = 6MHz (DAC) Excellent Gain/Phase Match 0.2 Phase, 0.05dB Gain at fIN = 25MHz (ADC) Internal/External Reference Option +2.7V to +3.3V Digital Output Level (TTL/CMOS Compatible) Multiplexed Parallel Digital Input/Output for ADCs/DACs Miniature 48-Pin Thin QFN Package (7mm 7mm) Evaluation Kit Available (Order MAX5865EVKIT)
MAX5866
The MAX5866 ultra-low-power, highly integrated analog front end is ideal for portable communication equipment such as handsets, PDAs, WLAN, and 3G wireless terminals. The MAX5866 integrates dual, 8-bit receive ADCs and dual, 10-bit transmit DACs while providing the highest dynamic performance at ultra-low power. The ADCs' analog I-Q input amplifiers are fully differential and accept 1V P-P full-scale signals. Typical I-Q channel phase matching is 0.2 and amplitude matching is 0.05dB. The ADCs feature 48dB SINAD and 70.1dBc spurious-free dynamic range (SFDR) at fIN = 25MHz and fCLK = 60MHz. The DACs' analog I-Q outputs are fully differential with 400mV full-scale output, and 1.4V common-mode level. Typical I-Q channel phase matching is 0.4 and gain matching is 0.1dB. The DACs also feature dual, 10-bit resolution with 64.2dBc SFDR, at fOUT = 6MHz and fCLK = 60MHz. The ADCs and DACs operate simultaneously or independently for frequency-division duplex (FDD) and time-division duplex (TDD) modes. A 3-wire serial interface controls power-down and transceiver modes of operation. The typical operating power is 96mW at fCLK = 60MHz with the ADCs and DACs operating simultaneously in transceiver mode. The MAX5866 features an internal 1.024V voltage reference that is stable over the entire operating power-supply range and temperature range. The MAX5866 operates on a +2.7V to +3.3V analog power supply and a +2.7V to +3.3V digital I/O power supply for logic compatibility. The quiescent current is 12mA in idle mode and 1A in shutdown mode. The MAX5866 is specified for the extended (-40C to +85C) temperature range and is available in a 48-pin thin QFN package.
Ordering Information
PART MAX5866ETM TEMP RANGE -40C to +85C PIN-PACKAGE 48 Thin QFN-EP* (7mm x 7mm)
*EP = Exposed paddle.
Functional Diagram
MAX5866
IA+ IAQA+ ADC QACLK ID+ IDQD+ QDREFP COM REFN REFIN REF AND BIAS DAC DAC DAC INPUT MUX ADC ADC OUTPUT MUX DA0-DA7
Applications
Narrowband/Wideband CDMA Handsets and PDAs Fixed/Mobile Broadband Wireless Modems 3G Wireless Terminals VSAT Modems
DD0-DD9
SERIAL INTERFACE AND SYSTEM CONTROL
DIN SCLK CS
Pin Configuration appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Ultra-Low-Power, High-DynamicPerformance, 60Msps Analog Front End MAX5866
ABSOLUTE MAXIMUM RATINGS
VDD to GND, OVDD to OGND................................-0.3V to +3.4V GND to OGND.......................................................-0.3V to +0.3V IA+, IA-, QA+, QA-, ID+, ID-, QD+, QD-, REFP, REFN, REFIN, COM to GND ..............................-0.3V to (VDD + 0.3V) DD0-DD9, SCLK, DIN, CS, CLK, DA0-DA7 to OGND .............................-0.3V to (OVDD + 0.3V) Continuous Power Dissipation (TA = +70C) 48-Pin Thin QFN (derate 26.3mW/C above +70C)..............................................................................2.1W Thermal Resistance JA .................................................+38C/W Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 3V, OVDD = 3.0V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 60MHz, 50% duty cycle, ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33F, Xcvr mode, unless otherwise noted. Typical values are at TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER POWER REQUIREMENTS Analog Supply Voltage Output Supply Voltage VDD OVDD ADC operating mode, fIN = 25MHz, fCLK = 60MHz, DAC operating mode, fOUT = 6MHz ADC operating mode (Rx), fIN = 25MHz, fCLK = 60MHz, DAC digital inputs at zero or OVDD VDD Supply Current DAC operating mode (Tx), fOUT = 6MHz, fCLK = 60MHz, ADC off Standby mode, DAC digital inputs and CLK at zero or OVDD Idle mode, DAC digital inputs at zero or OVDD, fCLK = 60MHz Shutdown mode, digital inputs and CLK at zero or OVDD, CS = OVDD ADC operating mode, fIN = 25MHz, fCLK = 60MHz, DAC operating mode, fOUT = 6MHz OVDD Supply Current Idle mode, DAC digital inputs at zero or OVDD, fCLK = 60MHz Shutdown mode, DAC digital inputs and CLK at zero or OVDD, CS = OVDD 1 9.9 108.4 A 1 2.7 2.7 32 3.0 3.3 VDD 38 V V SYMBOL CONDITIONS MIN TYP MAX UNITS
26.6 mA
17.5 2.0 14.5
A mA
2
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Ultra-Low-Power, High-DynamicPerformance, 60Msps Analog Front End
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 3.0V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 60MHz, 50% duty cycle, ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33F, Xcvr mode, unless otherwise noted. Typical values are at TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER ADC DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error DC Gain Matching Offset Matching Gain Temperature Coefficient Power-Supply Rejection ADC ANALOG INPUT Input Differential Range Input Common-Mode Voltage Range Input Impedance ADC CONVERSION RATE Maximum Clock Frequency Data Latency ADC DYNAMIC CHARACTERISTICS (Note 3) Signal-to-Noise Ratio Signal-to-Noise and Distortion Ratio Spurious-Free Dynamic Range Third-Harmonic Distortion Intermodulation Distortion Third-Order Intermodulation Distortion Total Harmonic Distortion SNR SINAD SFDR HD3 IMD IM3 THD fIN = 10MHz fIN = 25MHz fIN = 10MHz fIN = 25MHz fIN = 10MHz fIN = 25MHz fIN = 10MHz fIN = 25MHz f1 = 5.1MHz, -7dBFS; f2 = 5.2MHz, -7dBFS f1 = 5.1MHz, -7dBFS; f2 = 5.2MHz, -7dBFS fIN = 10MHz fIN = 25MHz 55.5 46.5 47 48.4 48.1 48.3 48 71.7 70.6 -73.7 -69.9 -68.5 -72.4 -71.2 -68.6 -55 dB dB dBc dBc dBc dBc dBc fCLK (Note 2) Channel I Channel Q 5 5.5 60 MHz Clock cycles RIN CIN Switched capacitor load VID Differential or single-ended inputs 0.512 VDD / 2 90 5 V V k pF PSRR Offset error (VDD 5%) Gain error (VDD 5%) INL DNL No missing codes over temperature Residual DC offset error Includes reference error 8 0.36 0.2 0.86 0.67 0.03 3 42 0.48 0.07 6 5 0.25 Bits LSB LSB %FS %FS dB LSB ppm/C LSB SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5866
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3
Ultra-Low-Power, High-DynamicPerformance, 60Msps Analog Front End MAX5866
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 3.0V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 60MHz, 50% duty cycle, ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33F, Xcvr mode, unless otherwise noted. Typical values are at TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER Full-Power Bandwidth Aperture Delay Aperture Jitter Overdrive Recovery Time ADC INTERCHANNEL CHARACTERISTICS Crosstalk Rejection Amplitude Matching Phase Matching DAC DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Zero-Scale Error Full-Scale Error DAC DYNAMIC PERFORMANCE DAC Conversion Rate Noise over Nyquist Glitch Impulse Spurious-Free Dynamic Range Total Harmonic Distortion (to Nyquist) Signal-to-Noise Ratio (to Nyquist) DAC-to-DAC Output Isolation Gain Mismatch Between DAC Outputs Phase Mismatch Between DAC Outputs SFDR THD SNR fCLK = 45MHz, fOUT = 2.2MHz fCLK = 60MHz, fOUT = 6MHz fCLK = 60MHz, fOUT = 6MHz fCLK = 60MHz, fOUT = 6MHz 58.5 ND (Note 2) fOUT = 6MHz, fCLK = 60MHz -130.8 10 69.5 64.2 -60.6 56 -56 60 Msps dBc/Hz pVs dBc dB dB N INL DNL Guaranteed monotonic Residual DC offset Include reference error -35 10 0.3 0.2 3 +35 Bits LSB LSB LSB LSB fINX = 5.5MHz at -0.5dBFS, fINY = 0.9MHz at -0.5dBFS (Note 5) fIN = 5.5MHz at -0.5dBFS (Note 6) fIN = 5.5MHz at -0.5dBFS (Note 6) -73 0.05 0.2 dB dB Degrees 1.5 x full-scale input SYMBOL FBW AIN = -0.5dBFS CONDITIONS MIN TYP 150 3.3 3.3 2 MAX UNITS MHz ns psRMS ns
DAC INTERCHANNEL CHARACTERISTICS fOUTX, Y = 6.0MHz, fOUTX, Y = 6.2MHz fOUT = 2.2MHz, fCLK = 60MHz fOUT = 2.2MHz, fCLK = 60MHz 70 0.1 0.4 dB dB Degrees
4
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Ultra-Low-Power, High-DynamicPerformance, 60Msps Analog Front End
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 3.0V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 60MHz, 50% duty cycle, ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33F, Xcvr mode, unless otherwise noted. Typical values are at TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER DAC ANALOG OUTPUT Full-Scale Output Voltage Output Common-Mode Range ADC-DAC INTERCHANNEL CHARACTERISTICS ADC-DAC Isolation ADC-DAC TIMING CHARACTERISTICS CLK Rise to I-ADC Channel-I Output Data Valid CLK Fall to Q-ADC Channel-Q Output Data Valid I-DAC Data to CLK Fall Setup Time Q-DAC Data to CLK Rise Setup Time CLK Fall to I-DAC Data Hold Time CLK Rise to Q-DAC Data Hold Time Clock Duty Cycle CLK Duty-Cycle Variation Digital Output Rise/Fall Time Falling Edge of CS to Rising Edge of First SCLK Time DIN to SCLK Setup Time DIN to SCLK Hold Time SCLK Pulse-Width High SCLK Pulse-Width Low SCLK Period SCLK to CS Setup Time CS High Pulse Width 20% to 80% SERIAL INTERFACE TIMING CHARACTERISTICS tCSS tDS tDH tCH tCL tCP tCS tCSW Figure 5 (Note 4) Figure 5 (Note 4) Figure 5 (Note 4) Figure 5 (Note 4) Figure 5 (Note 4) Figure 5 (Note 4) Figure 5 (Note 4) Figure 5 (Note 4) From shutdown to Rx mode, Figure 6, ADC settles to within 1dB Shutdown Wake-Up Time tWAKE,SD From shutdown to Tx mode, Figure 6, DAC settles to within 10 LSB error 10 10 0 25 25 50 0 80 ns ns ns ns ns ns ns ns tDOI tDOQ tDSI tDSQ tDHI tDHQ Figure 3 (Note 4) Figure 3 (Note 4) Figure 4 (Note 4) Figure 4 (Note 4) Figure 4 (Note 4) Figure 4 (Note 4) 3 3 9 9 -3 -3 50 10 2.0 4.9 6.2 8.5 8.5 ns ns ns ns ns ns % % ns ADC fINI = fINQ = 25MHz, DAC fOUTI = fOUTQ = 6MHz, fCLK = 60MHz 70 dB VFS 1.29 400 1. 5 mV V SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5866
MODE RECOVERY TIMING CHARACTERISTICS 10 s 40
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5
Ultra-Low-Power, High-DynamicPerformance, 60Msps Analog Front End MAX5866
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 3.0V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 60MHz, 50% duty cycle, ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33F, Xcvr mode, unless otherwise noted. Typical values are at TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS From idle to Rx mode with CLK present during idle, Figure 6, ADC settles to within 1dB SINAD Idle Wake-Up Time (with CLK) tWAKE,ST0 From idle to Tx mode with CLK present during idle, Figure 6, DAC settles to 10 LSB error From standby to Rx mode, Figure 6, ADC settles to within 1dB SINAD Standby Wake-Up Time tWAKE,ST1 From standby to Tx mode, Figure 6, DAC settles to 10 LSB error 10 MIN TYP 10 s MAX UNITS
10 s 40 10 10 0.256 -0.256 VDD / 2 V /2 VDD / 2 DD - 0.15 + 0.15 s s V V V V ppm/C mA mA
Enable Time from Xcvr or Tx to Rx Enable Time from Xcvr or Rx to Tx Positive Reference Negative Reference Common-Mode Output Voltage Differential Reference Output Differential Reference Temperature Coefficient Maximum REFP/REFN/COM Source Current Maximum REFP/REFN/COM Sink Current Reference Input Differential Reference Output Common-Mode Output Voltage Maximum REFP/REFN/COM Source Current Maximum REFP/REFN/COM Sink Current REFIN Input Resistance REFIN Input Current
tENABLE, Rx ADC settles to within 1dB SINAD tENABLE, Tx DAC settles to 10 LSB error VREFP - VCOM VREFN - VCOM VCOM VREF REFTC ISOURCE ISINK VREFP - VREFN
INTERNAL REFERENCE (REFIN = VDD; VREFP, VREFN, and VCOM are generated internally.)
+0.49
+0.512 +0.534 16 2 2
BUFFERED EXTERNAL REFERENCE (REFIN = 1.024V; VREFP, VREFN, and VCOM are generated internally.) VREFIN VDIFF VCOM ISOURCE ISINK VREFP - VREFN 1.024 0.512 VDD / 2 2 2 >500 -0.7 0.7 x OVDD V V V mA mA k A
DIGITAL INPUTS (CLK, SCLK, DIN, CS, DD0-DD9) Input High Threshold VINH DD0-DD9, CLK, SCLK, DIN, CS V
6
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Ultra-Low-Power, High-DynamicPerformance, 60Msps Analog Front End
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 3.0V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 60MHz, 50% duty cycle, ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33F, Xcvr mode, unless otherwise noted. Typical values are at TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER Input Low Threshold Input Leakage Input Capacitance DIGITAL OUTPUTS (DA0-DA7) Output Voltage Low Output Voltage High Tri-State Leakage Current Tri-State Output Capacitance VOL VOH ILEAK COUT 5 ISINK = 200A ISOURCE = 200A 0.8 x OVDD 5 0.2 x OVDD V V A pF SYMBOL VINL DIIN DCIN CONDITIONS DD0-DD9, CLK, SCLK, DIN, CS DD0-DD9, CLK, SCLK, DIN, CS = OGND or OVDD 5 MIN TYP MAX 0.3 x OVDD 5 UNITS V A pF
MAX5866
Note 1: Specifications from TA = +25C to +85C are guaranteed by production tests. Specifications from TA = +25C to -40C are guaranteed by design and characterization. Note 2: The minimum clock frequency for the MAX5866 is 40MHz. Note 3: SNR, SINAD, SFDR, HD3, and THD are based on a differential analog input voltage of -0.5dBFS referenced to the amplitude of the digital outputs. SINAD and THD are calculated using HD2 through HD6. Note 4: Guaranteed by design and characterization. Note 5: Crosstalk rejection is measured by applying a high-frequency test tone to one channel and a low-frequency tone to the second channel. FFTs are performed on each channel. The parameter is specified as the power ratio of the first and second channel FFT test tone bins. Note 6: Amplitude/phase matching is measured by applying the same signal to each channel, and comparing the magnitude and phase of the fundamental bin on the calculated FFT.
Typical Operating Characteristics
(VDD = 3V, OVDD = 3.0V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 60MHz 50% duty cycle, ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33F, Xcvr mode, TA = +25C, unless otherwise noted.)
ADC CHANNEL-IA FFT PLOT
MAX5866 toc01
ADC CHANNEL-QA FFT PLOT
MAX5866 toc02
ADC CHANNEL-IA TWO-TONE FFT PLOT
-10 -20 AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 -100 -110 f1 f2 fCLK = 60MHz f1 = 11.813MHz f2 = 12.795MHz AIA = -7dBFS PER TONE
MAX5866 toc03
0 -10 -20 AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 -100 -110 0 5 10 15 20 25 HD3 QA HD2 fCLK = 60MHz fIA = 12.499MHz fQA = 19.99MHz IA
0 -10 -20 AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 -100 -110
fCLK = 60MHz fIA = 12.499MHz fQA = 19.99MHz
0
QA
HD3
IA
HD2
30
0
5
FREQUENCY (MHz)
10 15 20 FREQUENCY (MHz)
25
30
0
5
10
15
20
25
30
FREQUENCY (MHz)
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7
Ultra-Low-Power, High-DynamicPerformance, 60Msps Analog Front End MAX5866
Typical Operating Characteristics (continued)
(VDD = 3V, OVDD = 3.0V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 60MHz 50% duty cycle, ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33F, Xcvr mode, TA = +25C, unless otherwise noted.)
ADC CHANNEL-QA TWO-TONE FFT PLOT
-10 -20 AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 -100 -110 0 5 10 15 20 25 30 FREQUENCY (MHz) f1 f2 fCLK = 60MHz f1 = 11.813MHz f2 = 12.795MHz AQA = -7dBFS PER TONE
MAX5866 toc04
ADC SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY
MAX5866 toc05
ADC SIGNAL-TO-NOISE AND DISTORTION RATIO vs. ANALOG INPUT FREQUENCY
49.5 49.0 SINAD (dB) 48.5 48.0 47.5 47.0 46.5 46.0
MAX5866 toc06
0
50.0 49.5 49.0 SNR (dB) 48.5 48.0 47.5 47.0 46.5 46.0 0 25 50 75 100
50.0
125
0
25
50
75
100
125
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ADC TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY
MAX5866 toc07
ADC SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY
MAX5866 toc08
ADC SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY
SINGLE ENDED 75 70
MAX5866 toc09
-40 -45 -50
80 75 70 SFDR (dBc)
80
SFDR (dBc)
THD (dB)
-55 -60 -65 -70 -75 -80 0 25 50 75 100 125 ANALOG INPUT FREQUENCY (MHz)
65 60 55 50
65 60 55 50 0 25 50 75 100 125 ANALOG INPUT FREQUENCY (MHz)
45 40 0 25 50 75 100 125 ANALOG INPUT FREQUENCY (MHz)
ADC SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT POWER
MAX5866 toc10
ADC SIGNAL-TO-NOISE AND DISTORTION RATIO vs. ANALOG INPUT POWER
MAX5866 toc11
ADC TOTAL HARMONIC DISTORTION vs. ANALOG INPUT POWER
-35 -40 -45 THD (dB) -50 -55 -60 fIN = 10.0732MHz
MAX5866 toc12
60 50 40 30 20 10 0
fIN = 10.0732MHz
60 50 40 SINAD (dB) 30 20 10 0
fIN = 10.0732MHz
-30
SNR (dB)
-65 -70 -75 -80 -24 -20 -16 -12 -8 -4 0 -24 -20 -16 -12 -8 -4 0 ANALOG INPUT POWER (dBFS) ANALOG INPUT POWER (dBFS)
-24
-20
-16
-12
-8
-4
0
ANALOG INPUT POWER (dBFS)
8
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Ultra-Low-Power, High-DynamicPerformance, 60Msps Analog Front End MAX5866
Typical Operating Characteristics (continued)
(VDD = 3V, OVDD = 3.0V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 60MHz 50% duty cycle, ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33F, Xcvr mode, TA = +25C, unless otherwise noted.)
ADC SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT POWER
MAX5866 toc13
ADC SIGNAL-TO-NOISE RATIO vs. SAMPLING RATE
MAX5866 toc14
ADC SIGNAL-TO-NOISE AND DISTORTION RATIO vs. SAMPLING RATE
fIN = 10.7MHz
MAX5866 toc15
80 75 70 65 SFDR (dBc)
fIN = 10.0732MHz
50 49 48
fIN = 10.7MHz
50
49 SINAD (dB)
55 50 45 40 35 30 -24 -20 -16 -12 -8 -4 0 ANALOG INPUT POWER (dBFS)
SNR (dB)
60
48
47 46 45 44 40 42 44 46 48 50 52 54 56 58 60 SAMPLING RATE (MHz)
47
46
45 40 42 44 46 48 50 52 54 56 58 60 SAMPLING RATE (MHz)
ADC TOTAL HARMONIC DISTORTION vs. SAMPLING RATE
MAX5866 toc16
ADC SPURIOUS-FREE DYNAMIC RANGE vs. SAMPLING RATE
MAX5866 toc17
ADC SIGNAL-TO-NOISE RATIO vs. CLOCK DUTY CYCLE
MAX5866 toc18
-50 -55 -60
fIN = 10.7MHz
80 75 70 SFDR (dBc) 65 60 55 50
50
fIN = 10.7MHz
49
THD (dB)
-65 -70 -75 -80 40 42 44 46 48 50 52 54 56 58 60 SAMPLING RATE (MHz)
SNR (dB)
48
47
46 fIN = 25MHz 45 40 42 44 46 48 50 52 54 56 58 60 SAMPLING RATE (MHz) 40 45 50 55 60 CLOCK DUTY CYCLE (%)
ADC SIGNAL-TO-NOISE AND DISTORTION RATIO vs. CLOCK DUTY CYCLE
MAX5866 toc19
ADC TOTAL HARMONIC DISTORTION vs. CLOCK DUTY CYCLE
MAX5866 toc20
ADC SPURIOUS-FREE DYNAMIC RANGE vs. CLOCK DUTY CYCLE
fIN = 25MHz 75 70
MAX5866 toc21
50
-50 fIN = 25MHz -55
80
49
THD (dB)
48
-60
SFDR (dBc) 40 50 55 45 CLOCK DUTY CYCLE (%) 60
SINAD (dB)
65 60
47
-65
46 fIN = 25MHz 45 40 45 50 55 60 CLOCK DUTY CYCLE (%)
-70
55 50 40 50 55 45 CLOCK DUTY CYCLE (%) 60
-75
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9
Ultra-Low-Power, High-DynamicPerformance, 60Msps Analog Front End MAX5866
Typical Operating Characteristics (continued)
(VDD = 3V, OVDD = 3.0V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 60MHz 50% duty cycle, ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33F, Xcvr mode, TA = +25C, unless otherwise noted.)
ADC OFFSET ERROR vs. TEMPERATURE
MAX5866 toc22
ADC GAIN ERROR vs. TEMPERATURE
MAX5866 toc23
SUPPLY CURRENT vs. SAMPLING RATE
Rx MODE ONLY fIN = 10MHz
MAX5866 toc24
2.0 1.5 1.0 OFFSET ERROR (%FS) 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -40 -15 10 35 60
1.0 0.8 0.6 GAIN ERROR (%FS) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
30 25 SUPPLY CURRENT (mA) 20 15 10 5 0 IOVDD
IDD
85
-40
-15
10
35
60
85
40
44
48
52
56
60
TEMPERATURE (C)
TEMPERATURE (C)
SAMPLING RATE (MHz)
DAC SPURIOUS-FREE DYNAMIC RANGE vs. SAMPLING RATE
MAX5866 toc25
DAC SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY
MAX5866 toc26
DAC SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT POWER
fOUT = 6MHz 80 70 SFDR (dBc) 60 50 40 30
MAX5866 toc27
70 69 68 67 SFDR (dBc) 66 65 64 63 62 61 60
80 75 70 SFDR (dBc) 65 60 55 50
90
fOUT = fCLK/10
40 42 44 46 48 50 52 54 56 58 60 SAMPLING RATE (MHz)
0
2
4
6
8
10
-30
-25
-20
-15
-10
-5
0
OUTPUT FREQUENCY (MHz)
OUTPUT POWER (dBFS)
DAC CHANNEL-ID SPECTRAL PLOT
MAX5866 toc28
DAC CHANNEL-QD SPECTRAL PLOT
-10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 fQD = 6MHz
MAX5866 toc29
DAC CHANNEL-ID TWO-TONE SPECTRAL PLOT
-10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 f1 f2 f1 = 4MHz, f2 = 4.5MHz, -7dBFS
MAX5866 toc30
0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 0 5 10 15 20
fID = 6MHz
0
0
25
30
0
5
10
15
20
25
30
0.5
5.0
9.5
14.0
18.5
23.0
27.5
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
10
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Ultra-Low-Power, High-DynamicPerformance, 60Msps Analog Front End MAX5866
Typical Operating Characteristics (continued)
(VDD = 3V, OVDD = 3.0V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 60MHz 50% duty cycle, ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33F, Xcvr mode, TA = +25C, unless otherwise noted.)
DAC CHANNEL-QD TWO-TONE SPECTRAL PLOT
MAX5866 toc31
SUPPLY CURRENT vs. SAMPLING RATE
MAX5866 toc33
ADC INTEGRAL NONLINEARITY
0.4 0.3 0.2 INL (LSB)
MAX5866 toc34
0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 0.5 5.0 9.5 14.0 18.5 23.0 27.5 FREQUENCY (MHz) f1 f2 f1 = 4MHz, f2 = 4.5MHz, -7dBFS
0.5
Xcvr MODE 30 SUPPLY CURRENT (mA) 25 20 15 10 5 0 IOVDD IDD fIN = 10MHz fOUT = 6MHz
0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5
40 42 44 46 48 50 52 54 56 58 60 SAMPLING RATE (MHz)
0
32
64
96
128 160 192 224 256
DIGITAL OUTPUT CODE
ADC DIFFERENTIAL NONLINEARITY
MAX5866 toc35
DAC INTEGRAL NONLINEARITY
0.8 0.6 0.4 INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
MAX5866 toc36
0.5 0.4 0.3 0.2 DNL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 32 64 96
1.0
128 160 192 224 256
0
128 256 384 512 640 768 896 1024 DIGITAL INPUT CODE
DIGITAL OUTPUT CODE
DAC DIFFERENTIAL NONLINEARITY
MAX5866 toc37
REFERENCE OUTPUT VOLTAGE vs. TEMPERATURE
VREFP - VREFN 0.515 VREFP - VREFN (V)
MAX5866 toc38
0.5 0.4 0.3 0.2 DNL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0
0.520
0.510
0.505
0.500 128 256 384 512 640 768 896 1024 DIGITAL INPUT CODE -40 -15 10 35 60 85 TEMPERATURE (C)
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11
Ultra-Low-Power, High-DynamicPerformance, 60Msps Analog Front End MAX5866
Pin Description
PIN 1 2, 8, 11, 33, 39, 43 3 4 5, 7, 12, 37, 42 6 9 10 13-16, 19-22 17 18 23-32 34 35 36 38 40, 41 44, 45 46 47 48 -- NAME REFP VDD IA+ IAGND CLK QAQA+ DA0-DA7 OGND OVDD DD0-DD9 DIN SCLK CS N.C. QD+, QDID-, ID+ REFIN COM REFN EP FUNCTION Upper Reference Voltage. Bypass with a 0.33F capacitor to GND as close to REFP as possible. Analog Supply Voltage. Bypass VDD to GND with a combination of a 2.2F capacitor in parallel with a 0.1F capacitor. Channel IA Positive Analog Input. For single-ended operation, connect signal source to IA+. Channel IA Negative Analog Input. For single-ended operation, connect IA- to COM. Analog Ground. Connect all pins to GND ground plane. Conversion Clock Input. Clock signal for both ADCs and DACs. Channel QA Negative Analog Input. For single-ended operation, connect QA- to COM. Channel QA Positive Analog Input. For single-ended operation, connect signal source to QA+. ADC Tri-State Digital Output Bits. DA7 is the most significant bit (MSB), and DA0 is the least significant bit (LSB). Output Driver Ground Output Driver Power Supply. Supply range from +2.7V to VDD to accommodate most logic levels. Bypass OVDD to OGND with a combination of a 2.2F capacitor in parallel with a 0.1F capacitor. DAC Digital Input Bits. DD9 is the MSB, and DD0 is the LSB. 3-Wire Serial-Interface Data Input. Data is latched on the rising edge of the SCLK. 3-Wire Serial-Interface Clock Input 3-Wire Serial-Interface Chip-Select Input. Apply logic low to enable the serial interface. No Connection DAC Channel-QD Differential Voltage Output DAC Channel-ID Differential Voltage Output Reference Input. Connect to VDD for internal reference. Common-Mode Voltage I/O. Bypass COM to GND with a 0.33F capacitor. Negative Reference I/O. Conversion range is (VREFP - VREFN). Bypass REFN to GND with a 0.33F capacitor. Exposed Paddle. Exposed paddle is internally connected to GND. Connect EP to the GND plane.
12
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Ultra-Low-Power, High-DynamicPerformance, 60Msps Analog Front End
Detailed Description
The MAX5866 integrates dual 8-bit receive ADCs and dual 10-bit transmit DACs while providing ultra-low power and highest dynamic performance at a conversion rate of 60Msps. The ADCs' analog input amplifiers are fully differential and accept 1VP-P full-scale signals. The DACs' analog outputs are fully differential with 400mV full-scale output range at 1.4V common mode. The MAX5866 includes a 3-wire serial interface to control operating modes and power management. The serial interface is SPITM and MICROWIRETM compatible. The MAX5866 serial interface selects shutdown, idle, standby, transmit, receive, and transceiver modes. The MAX5866 can operate in FDD or TDD applications by configuring the device for transmit, receive, or transceiver modes through a 3-wire serial interface. In TDD mode, the digital bus for receive ADC and transmit DAC can be shared to reduce the digital I/O to a single 10-bit parallel multiplexed bus. In FDD mode, the MAX5866 digital I/O can be configured for an 18-bit, parallel multiplexed bus to match the dual 8-bit ADC and dual 10-bit DAC. The MAX5866 features an internal precision 1.024V bandgap reference that is stable over the entire powersupply and temperature ranges.
MAX5866
INTERNAL BIAS S2a C1a S4a IA+ C2a S4c S1
COM S5a S3a
OUT
IAS4b C2b C1b S3b S2b INTERNAL BIAS INTERNAL BIAS S2a C1a S4a QA+ C2a S4c S1 S5b COM
OUT
HOLD TRACK
HOLD TRACK
CLK INTERNAL NONOVERLAPPING CLOCK SIGNALS
COM S5a S3a
OUT
MAX5866
OUT
QAS4b C2b C1b S3b S2b INTERNAL BIAS S5b COM
Figure 1. MAX5866 ADC Internal T/H Circuits SPI is a trademark of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. ______________________________________________________________________________________ 13
Ultra-Low-Power, High-DynamicPerformance, 60Msps Analog Front End MAX5866
Dual 8-Bit ADC
The ADC uses a seven-stage, fully differential, pipelined architecture that allows for high-speed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half clock cycle. Including the delay through the output latch, the total clock-cycle latency is 5 clock cycles for channel IA and 5.5 clock cycles for channel QA. The ADC's full-scale analog input range is VREF with a common-mode input range of VDD / 2 0.2V. VREF is the difference between VREFP and VREFN. See the Reference Configurations section for details. Input Track-and-Hold (T/H) Circuits Figure 1 displays a simplified functional diagram of the ADC's input T/H circuitry. In track mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b are closed. The fully differential circuits sample the input signals onto the two capacitors (C2a and C2b) through switches S4a and S4b. S2a and S2b set the common mode for the amplifier input, and open simultaneously with S1, sampling the input waveform. Switches S4a, S4b, S5a, and S5b are then opened before switches S3a and S3b connect capacitors C1a and C1b to the output of the amplifier and switch S4c is closed. The resulting differential voltages are held on capacitors C2a and C2b. The amplifiers charge capacitors C1a and C1b to the same values originally held on C2a and C2b. These values are then presented to the first-stage quantizers and isolate the pipelines from the fast-changing inputs. The wide input bandwidth T/H amplifiers allow the ADC to track and sample/hold analog inputs of high frequencies (> Nyquist). Both ADC inputs (IA+, QA+, IA-, and QA-) can be driven either differentially or single ended. Match the impedance of IA+ and IA-, as well as QA+ and QA-, and set the common-mode voltage to midsupply (VDD / 2) for optimum performance. ADC Digital Output Data (DA0-DA7) DA0-DA7 are the ADCs' digital logic outputs. The logic level is set by OVDD from +2.7V to VDD. The digital output coding is offset binary (Table 1, Figure 2). The capacitive load on digital outputs DA0-DA7 should be kept as low as possible (<15pF) to avoid large digital currents feeding back into the analog portion of the MAX5866 and degrading its dynamic performance. Buffers on the digital outputs isolate them from heavy capacitive loads. Adding 100 resistors in series with the digital outputs close to the MAX5866 helps improve ADC performance. Refer to the MAX5865 EV kit schematic for an example of the digital outputs driving a digital buffer through 100 series resistors.
Table 1. Output Codes vs. Input Voltage
DIFFERENTIAL INPUT VOLTAGE
VREF x VREF x VREF x VREF x
- VREF x - VREF x - VREF x
DIFFERENTIAL INPUT (LSB) 127 (+full scale - 1LSB) 126 (+full scale - 2LSB) +1 0 (bipolar zero) -1 -127 (-full scale + 1LSB) -128 (-full scale)
OFFSET BINARY (DA7-DA0) 1111 1111 1111 1110 1000 0001 1000 0000 0111 1111 0000 0001 0000 0000
OUTPUT DECIMAL CODE 255 254 129 128 127 1 0
127 128 126 128 1 128 0 128 1 128 127 128 128 128
14
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Ultra-Low-Power, High-DynamicPerformance, 60Msps Analog Front End
ADC System Timing Requirements Figure 3 shows the relationship between the clock, analog inputs, and the resulting output data. Channel IA (CHI) and channel QA (CHQ) are simultaneously sampled on the rising edge of the clock signal (CLK) and the resulting data is multiplexed at the DA0-DA7 out2 x VREF 256 VREF 1111 1111 1111 1110 1111 1101 VREF = VREFP - VREFN VREF
puts. CHI data is updated on the rising edge and CHQ data is updated on the falling edge of the CLK. Including the delay through the output latch, the total clock-cycle latency is 5 clock cycles for CHI and 5.5 clock cycles for CHQ.
MAX5866
Dual 10-Bit DAC
The 10-bit DACs are capable of operating with clock speeds up to 60MHz. The DAC's digital inputs, DD0-DD9, are multiplexed on a single 10-bit bus. The voltage reference determines the data converters' full-scale output voltages. See the Reference Configurations section for setting reference voltage. The DACs utilize a current-array technique with a 1mA (with 1.024V reference) full-scale output current driving a 400 internal resistor resulting in a 400mV full-scale differential output voltage. The MAX5866 is designed for differential output only and is not intended for single-ended application. The analog outputs are biased at 1.4V common mode and designed to drive a differential input stage with input impedance 70k. This simplifies the analog interface between RF quadrature upconverters and the MAX5866. RF upconverters require a 1.3V to 1.5V common-mode bias. The internal DC common-mode bias eliminates discrete levelsetting resistors and code-generated level-shifting while preserving the full dynamic range of each transmit DAC. Table 2 shows the output voltage vs. input code.
1 LSB =
OFFSET BINARY OUTPUT CODE (LSB)
1000 0001 1000 0000 0111 1111
0000 0011 0000 0010 0000 0001 0000 0000
-128 -127 -126 -125 -1 0 +1
+125 +126 +127 +128
(COM) INPUT VOLTAGE (LSB)
Figure 2. ADC Transfer Function
5 CLOCK-CYCLE LATENCY (CHI), 5.5 CLOCK-CYCLE LATENCY (CHQ)
CHI
CHQ
CLK
tDOQ DA0-DA7 D0Q D1I
tDOI D1Q D2I D2Q D3I D3Q D4I D4Q D5I D5Q D6I D6Q
Figure 3. ADC System Timing Diagram
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VREF
VREF (COM)
15
Ultra-Low-Power, High-DynamicPerformance, 60Msps Analog Front End MAX5866
Table 2. DAC Output Voltage vs. Input Codes (Internal Reference Mode VREFDAC = 1.024V, External Reference Mode VREFDAC = VREFIN)
DIFFERENTIAL OUTPUT VOLTAGE
VREFDAC 1023 x 2.56 1023 VREFDAC 1021 x 2.56 1023 3 VREFDAC x 2.56 1023 1 VREFDAC x 2.56 1023
- VREFDAC
OFFSET BINARY (DD0-DD9) 11 1111 1111 11 1111 1110 10 0000 0001 10 0000 0000 01 1111 1111 00 0000 0001 00 0000 0000
INPUT DECIMAL CODE 1023 1022 513 512 511 1 0
2.56
- VREFDAC
x x x
1 1023 1021 1023 1023 1023
2.56
- VREFDAC
2.56
CLK tDSQ DD0-DD9 Q: N - 2 I: N - 1 tDSI ID N-2 tDHQ Q: N - 1 I: N tDHI N-1 N Q: N I: N + 1
QD
N-2
N-1
N
Figure 4. DAC System Timing Diagram
DAC Timing Figure 4 shows the relationship between the clock, input data, and analog outputs. Data for the I channel is latched on the falling edge of the clock signal, and Qchannel data is latched on the rising edge of the clock signal. Both I and Q outputs are simultaneously updated on the next rising edge of the clock signal.
3-Wire Serial Interface and Operation Modes
The 3-wire serial interface controls the MAX5866 operation modes. Upon power-up, the MAX5866 must be programmed to operate in the desired mode. Use the 3-wire serial interface to program the device for the shutdown, idle, standby, Rx, Tx, or Xcvr mode. An 8-bit data register sets the operation modes as shown in Table 3. The serial interface remains active in all six modes.
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Ultra-Low-Power, High-DynamicPerformance, 60Msps Analog Front End MAX5866
Table 3. MAX5866 Operation Modes
FUNCTION DESCRIPTION Device shutdown. REF is off, ADCs are off, and the ADC bus is tri-stated; DACs are off and the DAC input bus must be set to zero or OVDD. REF and CLK are on, ADCs are off, and the ADC bus is tri-stated; DACs are off and the DAC input bus must be set to zero or OVDD. REF is on, ADCs are on; DACs are off, and the DAC input bus must be set to zero or OVDD. REF is on, ADCs are off, and the ADC bus is tri-stated; DACs are on. REF is on, ADCs and DACs are on. REF is on, ADCs are off, and the ADC bus is tri-stated; DACs are off and the DAC input bus must be set to zero or OVDD. D7 (MSB) D6 D5 D4 D3 D2 D1 D0
Shutdown
X
X
X
X
X
0
0
0
Idle
X
X
X
X
X
0
0
1
Rx
X
X
X
X
X
0
1
0
Tx Xcvr
X X
X X
X X
X X
X X
0 1
1 0
1 0
Standby
X
X
X
X
X
1
0
1
X = Don't care.
Shutdown mode offers the most dramatic power savings by shutting down all the analog sections of the MAX5866 and placing the ADCs' digital outputs in tristate mode. When the ADCs' outputs transition from tristate to on, the last converted word is placed on the digital outputs. The DACs' digital bus inputs must be zero or OVDD because the bus is not internally pulled up. The DACs' previously stored data is lost when coming out of shutdown mode. The wake-up time from shutdown mode is dominated by the time required to charge the capacitors at REFP, REFN, and COM. In internal reference mode and buffered external reference mode, the wake-up time is typically 40s to enter Xcvr mode, 10s to enter Rx mode, and 40s to enter Tx MODE. In idle mode, the reference and clock distribution circuits are powered, but all other functions are off. The ADCs' outputs are forced to tri-state. The DACs' digital bus inputs must be zero or OVDD, because the bus is not internally pulled up. The wake-up time required for the device to become fully operational from idle mode is 10s. When the ADCs' outputs transition from tri-state to on, the last converted word is placed on the digital outputs. In the idle mode, the supply current is lowered
QSPI is a trademark of Motorola, Inc.
if the clock input is set to zero or OVDD; however, the wake-up time extends to 40s. In standby mode, only the ADCs' reference is powered; the rest of the device's functions are off. The pipeline ADCs are off and DA0 to DA7 are in tri-state mode. The DACs' digital bus inputs must be zero or OV DD because the bus is not internally pulled up. The wakeup time from standby mode to the Xcvr mode is dominated by the 40s required to activate the pipeline ADCs and DACs. When the ADC outputs transition from tri-state to active, the last converted word is placed on the digital outputs. The serial digital interface is a standard 3-wire connection compatible with SPI/QSPITM/MICROWIRE/DSP interfaces. Set CS low to enable the serial data loading at DIN. Following the CS high-to-low transition, data is shifted synchronously, MSB first, on the rising edge of the serial clock (SCLK). After 8 bits are loaded into the serial input register, data is transferred to the latch. CS must transition high for a minimum of 80ns before the next write sequence. The SCLK can idle either high or low between transitions. Figure 5 shows the detailed timing diagram of the 3-wire serial interface.
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17
Ultra-Low-Power, High-DynamicPerformance, 60Msps Analog Front End MAX5866
tCSW CS tCSS tCP tCH tCL tCS
SCLK tDS DIN MSB tDH LSB
Figure 5. 3-Wire Serial Interface Timing Diagram
CS
SCLK
DIN
8-BIT DATA tWAKE, SD, ST_ (Rx) OR tENABLE, Rx
DAO-DA7
ADC DIGITAL OUTPUT. SINAD SETTLES WITHIN 1dB
ID/QD
DAC ANALOG OUTPUT. OUTPUT SETTLES TO 10 LSB ERROR tWAKE, SD, ST_ (Tx) OR tENABLE TX
Figure 6. MAX5866 Mode Recovery Timing Diagram
Mode Recovery Timing Figure 6 shows the mode recovery timing diagram. tWAKE is the wake-up time when exiting shutdown, idle, or standby mode and entering into Rx, Tx, or Xcvr mode. tENABLE is the recovery time when switching between any Rx, Tx, or Xcvr mode. tWAKE or tENABLE is the time for the ADC to settle within 1dB of specified SINAD performance and DAC settling to 10 LSB error. tWAKE or tENABLE times are measured after the 8-bit serial command is latched into the MAX5866 by CS transitioning high. tENABLE for Xcvr mode is dominated by the DAC wake-up time. The recovery time is 10s to switch between Xcvr, Tx, or Rx modes. The recovery time is 40s to switch from shutdown or standby mode to Xcvr mode.
System Clock Input (CLK)
CLK input is shared by both the ADCs and DACs. It accepts a CMOS-compatible signal level set by OVDD from +2.7V to VDD. Since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (<2ns). Specifically, sampling occurs on the rising edge of the clock signal, requiring this edge to provide the lowest possible jitter. Any significant clock jitter limits the SNR performance of the on-chip ADCs as follows: 1 SNR = 20 x log 2 x x tIN x t AJ where fIN represents the analog input frequency and tAJ is the time of the clock jitter.
18
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Ultra-Low-Power, High-DynamicPerformance, 60Msps Analog Front End
Clock jitter is especially critical for undersampling applications. Consider the clock input as an analog input and route away from any analog input or other digital signal lines. The MAX5866 clock input operates with an OVDD / 2 voltage threshold and accepts a 50% 10% duty cycle.
Applications Information
Using Balun Transformer AC-Coupling
An RF transformer (Figure 7) provides an excellent solution to convert a single-ended signal source to a fully differential signal for optimum ADC performance. Connecting the center tap of the transformer to COM provides a VDD / 2 DC level shift to the input. A 1:1 transformer can be used, or a step-up transformer can be selected to reduce the drive requirements. In general, the MAX5866 provides better SFDR and THD with fully differential input signals than single-ended signals, especially for high input frequencies. In differential mode, even-order harmonics are lower as both inputs (IA+, IA-, QA+, QA-) are balanced, and each of the ADC inputs only requires half the signal swing compared to single-ended mode. Figure 8 shows an RF transformer converting the MAX5866 DACs' differential analog outputs to single ended.
25 IA+ 0.1F VIN COM 0.33F 0.1F 22pF
MAX5866
Reference Configurations
The MAX5866 features an internal precision 1.024V bandgap reference that is stable over the entire powersupply and temperature range. The REFIN input provides two modes of reference operation. The voltage at REFIN (VREFIN) sets reference operation mode (Table 4). In internal reference mode, connect REFIN to VDD. VREF is an internally generated 0.512V. COM, REFP, and REFN are low-impedance outputs with VCOM = VDD / 2, VREFP = VDD / 2 + VREF / 2, and VREFN = VDD / 2 - VREF / 2. Bypass REFP, REFN, and COM each with a 0.33F capacitor. Bypass REFIN to GND with a 0.1F capacitor. In buffered external reference mode, apply 1.024V 10% at REFIN. In this mode, COM, REFP, and REFN are low-impedance outputs with V COM = V DD / 2, VREFP = VDD / 2 + VREFIN / 4, and VREFN = VDD / 2 VREFIN / 4. Bypass REFP, REFN, and COM each with a 0.33F capacitor. Bypass REFIN to GND with a 0.1F capacitor. In this mode, the DAC's full-scale output voltage and common-mode voltage are proportional to the external reference. For example, if the V REFIN is increased by 10% (max), the DACs' full-scale output voltage is also increased by 10% or to 440mV, and the common-mode voltage increases by 10%.
IA25 22pF
Table 4. Reference Modes
VREFIN REFERENCE MODE Internal reference mode. VREF is internally generated to be 0.512V. Bypass REFP, REFN, and COM each with a 0.33F capacitor. Buffered external reference mode. An external 1.024V 10% reference voltage is applied to REFIN. VREF is internally generated to be VREFIN / 2. Bypass REFP, REFN, and COM each with a 0.33F capacitor. Bypass REFIN to GND with a 0.1F capacitor.
VIN 0.1F
MAX5866
25 QA+ 22pF
>0. 8 x VDD
0.33F
0.1F
QA25 22pF
1.024V 10%
Figure 7. Balun-Transformer-Coupled Single-Ended-toDifferential Input Drive for ADCs
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19
Ultra-Low-Power, High-DynamicPerformance, 60Msps Analog Front End MAX5866
Using Op-Amp Coupling
ID+ VOUT
MAX5866
ID-
QD+
VOUT
QD-
Figure 8. Balun-Transformer-Coupled Differential-to-SingleEnded Output Drive for DACs
REFP
Drive the MAX5866 ADCs with op amps when a balun transformer is not available. Figures 9 and 10 show the ADCs being driven by op amps for AC-coupled singleended, and DC-coupled differential applications. Amplifiers such as the MAX4354/MAX4454 provide high speed, high bandwidth, low noise, and low distortion to maintain the input-signal integrity. Figure 10 can also be used to interface with the DAC differential analog outputs to provide gain or buffering. The DAC differential analog outputs cannot be used in singleended mode because of the internally generated 1.4VDC common-mode level. Also, the DAC analog outputs are designed to drive a differential input stage with input impedance 70k. If single-ended outputs are desired, use an amplifier to provide differential-tosingle-ended conversion and select an amplifier with proper input common-mode voltage range.
FDD and TDD Modes
The MAX5866 can be used in diverse applications operating FDD or TDD modes. The MAX5866 operates in Xcvr mode for FDD applications such as WCDMA3GPP (FDD) and 4G technologies. Also, the MAX5866 can switch between Tx and Rx modes for TDD applications like TD-SCDMA, WCDMA-3GPP (TDD), IEEE 802.11a/b/g, and IEEE 802.16. In FDD mode, the ADC and DAC operate simultaneously. The ADC bus and DAC bus are dedicated and must be connected in 18-bit parallel (8-bit ADC and 10-bit DAC) to the digital baseband processor. Select Xcvr mode through the 3-wire serial interface and use the conversion clock to latch data. In FDD mode, the MAX5866 uses 96mW power at fCLK = 60MHz. This is the total power of the ADC and DAC operating simultaneously. In TDD mode, the ADC and DAC operate independently. The ADC and DAC bus are shared and can be connected together, forming a single 10-bit parallel bus to the digital baseband processor. Using the 3-wire serial interface, select between Rx mode to enable the ADC and Tx mode to enable the DAC. When operating in Rx mode, the DAC does not transmit because the core is disabled and in Tx mode, the ADC bus is tri-state. This eliminates any unwanted spurious emissions and prevents bus contention. In TDD mode, the MAX5866 uses 80mW power in Rx mode at fCLK = 60MHz, and the DAC uses 52.5mW in Tx mode.
VIN 100
1k 0.1F
RISO 50 INA+ CIN 22pF
1k
COM REFN 0.1F RISO 50 100 INACIN 22pF REFP
MAX5866
RISO 50 INB+ CIN 22pF
VIN
0.1F
1k
100
1k
REFN
0.1F RISO 50
100
INBCIN 22pF
Figure 9. Single-Ended Drive for ADCs
20
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Ultra-Low-Power, High-DynamicPerformance, 60Msps Analog Front End MAX5866
R4 600 R5 600
R1 600
RISO 22 INACIN 5pF
MAX5866
R2 600 R6 600 R3 600 R8 600 R9 600 R7 600 COM
RISO 22 CIN 5pF INA+
R10 600
R11 600
Figure 10. ADC DC-Coupled Differential Drive
CLK ADC ADC OUTPUT MUX T/R MAX2820 ADC
10-BIT DAC DAC INPUT MUX DAC
MAX5866
SERIAL BUS
Figure 11. Typical Application Circuit for TDD
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DIGITAL BASEBAND PROCESSOR
21
Ultra-Low-Power, High-DynamicPerformance, 60Msps Analog Front End
Figure 11 illustrates the MAX5866 working with the MAX2820 in TDD mode to provide a complete 802.11b radio front-end solution. Because the MAX5866 DAC has full differential analog outputs with a common-mode level of 1.4V, and the ADC has wide-input common-mode range, it can interface directly with RF transceivers while eliminating discrete components and amplifiers used for level-shifting circuits. Also, the DAC's full dynamic range is preserved because the internally generated commonmode level eliminates code-generated level shifting or attenuation due to resistor level shifting. The MAX5866 ADC has 1VP-P full-scale range and accepts input common-mode levels of VDD / 2 (200mV). These features simplify the analog interface between RF quadrature demodulator and ADC while eliminating discrete gain amplifiers and level-shifting components. the MAX5866 exposed backside paddle to the GND plane. Join the two ground planes at a single point so the noisy digital ground currents do not interfere with the analog ground plane. The ideal location for this connection can be determined experimentally at a point along the gap between the two ground planes. Make this connection with a low-value, surface-mount resistor (1 to 5), a ferrite bead, or a direct short. Alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated from any noisy digital system's ground plane (e.g., downstream output buffer or DSP ground plane). Route high-speed digital signal traces away from sensitive analog traces. Make sure to isolate the analog input lines to each respective converter to minimize channel-to-channel crosstalk. Keep all signal lines short and free of 90 turns.
MAX5866
Grounding, Bypassing, and Board Layout
The MAX5866 requires high-speed board layout design techniques. Refer to the MAX5865 EV kit data sheet for a board layout reference. Locate all bypass capacitors as close to the device as possible, preferably on the same side of the board as the device, using surfacemount devices for minimum inductance. Bypass VDD to GND with a 0.1F ceramic capacitor in parallel with a 2.2F capacitor. Bypass OVDD to OGND with a 0.1F ceramic capacitor in parallel with a 2.2F capacitor. Bypass REFP, REFN, and COM each to GND with a 0.33F ceramic capacitor. Bypass REFIN to GND with a 0.1F capacitor. Multilayer boards with separated ground and power planes yield the highest level of signal integrity. Use a split ground plane arranged to match the physical location of the analog ground (GND) and the digital output driver ground (OGND) on the device package. Connect
7 6 ANALOG OUTPUT VALUE 5 4 3 2 1 0 000 001 010 011 100 101 110 111 DIGITAL INPUT CODE AT STEP 001 (1/4 LSB ) AT STEP 011 (1/2 LSB )
Dynamic Parameter Definitions
ADC and DAC Static Parameter Definitions
Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the device are measured using the end-point method. (DAC Figure 12a). Differential Nonlinearity (DNL) Differential nonlinearity is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes (ADC) and a monotonic transfer function (ADC and DAC) (DAC Figure 12b).
6 ANALOG OUTPUT VALUE 5 4 3 1 LSB 2 1 0 000 001 010 011 100 101 DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR (+1/4 LSB) 1 LSB DIFFERENTIAL LINEARITY ERROR (-1/4 LSB)
Figure 12a. Integral Nonlinearity 22
Figure 12b. Differential Nonlinearity
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Ultra-Low-Power, High-DynamicPerformance, 60Msps Analog Front End
ADC Offset Error Ideally, the midscale transition occurs at 0.5 LSB above midscale. The offset error is the amount of deviation between the measured transition point and the ideal transition point. DAC Offset Error Offset error (Figure 12a) is the difference between the ideal and actual offset point. The offset point is the output value when the digital input is midscale. This error affects all codes by the same amount and usually can be compensated by trimming. ADC Gain Error Ideally, the ADC full-scale transition occurs at 1.5 LSB below full scale. The gain error is the amount of deviation between the measured transition point and the ideal transition point with the offset error removed.
MAX5866
CLK
ANALOG INPUT tAD tAJ SAMPLED DATA (T/H)
T/H
TRACK
HOLD
TRACK
Figure 13. T/H Aperture Timing
ADC Dynamic Parameter Definitions
Aperture Jitter Figure 13 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay. Aperture Delay Aperture delay (tAD) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (Figure 13). Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error) and results directly from the ADC's resolution (N bits): SNR(max) = 6.02dB x N + 1.76dB (in dB) In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first five harmonics, and the DC offset. Signal-to-Noise Plus Distortion (SINAD) SINAD is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental and the DC offset. Effective Number of Bits (ENOB) ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC's error consists of quantization noise only. ENOB for a full-scale sinusoidal input waveform is computed from: ENOB = (SINAD - 1. 76) / 6.02
Total Harmonic Distortion (THD) THD is typically the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as: (V22 + V32 + V42 + V52 + V62 THD = 20log V1 )
where V1 is the fundamental amplitude and V2-V6 are the amplitudes of the 2nd- through 6th-order harmonics. Third Harmonic Distortion (HD3) HD3 is defined as the ratio of the RMS value of the third harmonic component to the fundamental input signal. Spurious-Free Dynamic Range (SFDR) SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest spurious component, excluding DC offset. Intermodulation Distortion (IMD) IMD is the total power of the intermodulation products relative to the total input power when two tones, f1 and f2, are present at the inputs. The intermodulation products are (f1 f2), (2 f1), (2 f2), (2 f1 f2), (2 f2 f1). The individual input tone levels are at -7dBFS. 3rd-Order Intermodulation (IM3) IM3 is the power of the worst third-order intermodulation product relative to the input power of either input tone when two tones, f 1 and f 2 , are present at the inputs. The 3rd-order intermodulation products are (2 x f1 f2), (2 f2 f1). The individual input tone levels are at -7dBFS.
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23
Ultra-Low-Power, High-DynamicPerformance, 60Msps Analog Front End MAX5866
Power-Supply Rejection Power-supply rejection is defined as the shift in offset and gain error when the power supply is changed 5%. Small-Signal Bandwidth A small -20dBFS analog input signal is applied to an ADC in such a way that the signal's slew rate does not limit the ADC's performance. The input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased by 3dB. Note that the T/H performance is usually the limiting factor for the small-signal input bandwidth. Full-Power Bandwidth A large -0.5dBFS analog input signal is applied to an ADC, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by 3dB. This point is defined as the fullpower bandwidth frequency.
REFN TOP VIEW COM REFIN
Pin Configuration
GND QDQD+
48
47
46
45
44
43
42
41
40
39
38
37 36 35 34 33 32 31
GND
VDD N.C.
ID+ IDVDD
REFP VDD IA+ IAGND CLK GND VDD QAQA+ VDD GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
CS SCLK DIN VDD DD9 DD8 DD7 DD6 DD5 DD4 DD3 DD2
MAX5866
30 29 28 27 26 25
DAC Dynamic Parameter Definitions
Total Harmonic Distortion THD is the ratio of the RMS sum of the output harmonics up to the Nyquist frequency divided by the fundamental: (V22 + V32 + ...+ Vn2 ) THD = 20log V1
DA1 DA2 DA3 OGND OVDD DA4
DA5 DA6
QFN
where V1 is the fundamental amplitude and V2 through Vn are the amplitudes of the 2nd through nth harmonic up to the Nyquist frequency. Spurious-Free Dynamic Range Spurious-free dynamic range (SFDR) is the ratio of RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest distortion component up to the Nyquist frequency excluding DC.
Chip Information
TRANSISTOR COUNT: 16,765 PROCESS: CMOS
24
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DA7 DD0 DD1
DA0
Ultra-Low-Power, High-DynamicPerformance, 60Msps Analog Front End MAX5866
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
D2 D D/2 k
C L
b D2/2
E/2 E2/2 E (NE-1) X e
C L
E2
k L DETAIL A e (ND-1) X e
C L
C L
L
L
e
e
A1
A2
A
TITLE:
SEMICONDUCTOR
PROPRIETARY INFORMATION
DALLAS
PACKAGE OUTLINE 32, 44, 48L THIN QFN, 7x7x0.8 mm
DOCUMENT CONTROL NO. REV.
APPROVAL
21-0144
C
1
2
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32, 44, 48L QFN.EPS
25
Ultra-Low-Power, High-DynamicPerformance, 60Msps Analog Front End MAX5866
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
SEMICONDUCTOR
PROPRIETARY INFORMATION TITLE:
DALLAS
PACKAGE OUTLINE 32, 44, 48L THIN QFN, 7x7x0.8 mm
DOCUMENT CONTROL NO. REV.
APPROVAL
21-0144
C
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
26 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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